[all-commits] [llvm/llvm-project] b9780f: [DAGCombine] Don't check the legality of type when...

[QingShan Zhang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b9780f4f80ba82c6271b6b87fbfe6ea32d154e49
      https://github.com/llvm/llvm-project/commit/b9780f4f80ba82c6271b6b87fbfe6ea32d154e49
  Author: QingShan Zhang <qshanz at cn.ibm.com>
  Date:   2020-01-06 (Mon, 06 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll

  Log Message:
  -----------
  [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG

This is the DAG node for SIGN_EXTEND_INREG :

t21: v4i32 = sign_extend_inreg t18, ValueType:ch:v4i16

It has two operands. The first one is the value it want to extend, and the second
one is the type to specify how to extend the value. For this example, it means
that, it is signed extend the t18(v4i32) from v4i16 to v4i32. That is
the semantics of c code:

vector int foo(vector int m) {
   return m << 16 >> 16;
}

And it could be any vector type that hardware support the operation, though
the type 'v4i16' is NOT legal for the target. When we are trying to combine
the srl + sra, what we did now is calling the TLI.isOperationLegal(), which
will also check the legality of the type. That doesn't make sense.

Differential Revision: https://reviews.llvm.org/D70230