[all-commits] [llvm/llvm-project] e3bd01: [X86][SSE] Combine combineLogicBlendIntoConditiona...
Simon Pilgrim via All-commits
all-commits at lists.llvm.org
Sun Jan 5 10:54:03 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: e3bd0118903ccb545ca5cb2641646eb66ae8180e
https://github.com/llvm/llvm-project/commit/e3bd0118903ccb545ca5cb2641646eb66ae8180e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2020-01-05 (Sun, 05 Jan 2020)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/vector-blend.ll
Log Message:
-----------
[X86][SSE] Combine combineLogicBlendIntoConditionalNegate for VSELECT nodes (PR43660)
Attempt to use combineLogicBlendIntoConditionalNegate for (select M, (sub 0, X), X) -> (sub (xor X, M), M)
We limit this to cases that can't easily replace the VSELECT with a shuffle (non-constant masks) or where a BLENDV is likely to occur (which tends to result in slower codegen).
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