[all-commits] [llvm/llvm-project] 2133d3: [DAGCombine] Initialize the default operation acti...

[QingShan Zhang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2133d3c5586b1a782e4d8e2a34c9f501499705cf
      https://github.com/llvm/llvm-project/commit/2133d3c5586b1a782e4d8e2a34c9f501499705cf
  Author: QingShan Zhang <qshanz at cn.ibm.com>
  Date:   2020-01-03 (Fri, 03 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    M llvm/test/CodeGen/ARM/signext-inreg.ll
    A llvm/test/CodeGen/Hexagon/signext-inreg.ll
    M llvm/test/CodeGen/Thumb2/mve-sext.ll

  Log Message:
  -----------
  [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

For now, we didn't set the default operation action for SIGN_EXTEND_INREG for
vector type, which is 0 by default, that is legal. However, most target didn't
have native instructions to support this opcode. It should be set as expand by
default, as what we did for ANY_EXTEND_VECTOR_INREG.

Differential Revision: https://reviews.llvm.org/D70000