[all-commits] [llvm/llvm-project] a5a141: [ARM] MVE sink ICmp test. NFC

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a5a141544d0b3ce64c97ef9bb88ae5231e427b9f
      https://github.com/llvm/llvm-project/commit/a5a141544d0b3ce64c97ef9bb88ae5231e427b9f
  Author: David Green <david.green at arm.com>
  Date:   2019-12-30 (Mon, 30 Dec 2019)

  Changed paths:
    A llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll

  Log Message:
  -----------
  [ARM] MVE sink ICmp test. NFC


  Commit: b4abe7afbf5272d56ec8adb39fdccf1e2df48a88
      https://github.com/llvm/llvm-project/commit/b4abe7afbf5272d56ec8adb39fdccf1e2df48a88
  Author: David Green <david.green at arm.com>
  Date:   2019-12-30 (Mon, 30 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/MVETailPredication.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll

  Log Message:
  -----------
  [ARM] Sink splat to ICmp

This adds ICmp to the list of instructions that we sink a splat to in a
loop, allowing the register forms of instructions to be selected more
often. It does not add FCmp yet as the results look a little odd, trying
to keep the register in an float reg and having to move it back to a GPR.

Differential Revision: https://reviews.llvm.org/D70997


Compare: https://github.com/llvm/llvm-project/compare/948e745270de...b4abe7afbf52