[all-commits] [llvm/llvm-project] d1b51c: [PowerPC] Modify the hasSideEffects of some VSX in...

[zhangkangcool via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d1b51c5de7a0b7a7d81c3b520614a139eb0160d2
      https://github.com/llvm/llvm-project/commit/d1b51c5de7a0b7a7d81c3b520614a139eb0160d2
  Author: Kang Zhang <shkzhang at cn.ibm.com>
  Date:   2019-12-28 (Sat, 28 Dec 2019)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

  Log Message:
  -----------
  [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0

Summary:
If we didn't set the value for hasSideEffects bit in our td file,  `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
Below 6 instructions don't set the hasSideEffects flag and don't have match
pattern, so their hasSideEffects flag will be set true by llvm-tblgen.

But in fact below instructions don't modify any special register and don't have
other SideEffects, they shouldn't have SideEffects.
This patch is to modify the hasSideEffects of below instructions from 1 to 0.

```
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX
VSPLTBs
VSPLTHs
```

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D71391