[all-commits] [llvm/llvm-project] a37e95: AMDGPU: Use correct DebugLoc

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a37e958558c0e0e189a677cfd02beb2aa1ac81bb
      https://github.com/llvm/llvm-project/commit/a37e958558c0e0e189a677cfd02beb2aa1ac81bb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-27 (Fri, 27 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

  Log Message:
  -----------
  AMDGPU: Use correct DebugLoc


  Commit: ed9a56b0f2587fb14068a98f6dfa83c8f92105f5
      https://github.com/llvm/llvm-project/commit/ed9a56b0f2587fb14068a98f6dfa83c8f92105f5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-27 (Fri, 27 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Select some 128-bit load/stores


  Commit: e088846712a6dfdc43328d4a81abb96452c0b456
      https://github.com/llvm/llvm-project/commit/e088846712a6dfdc43328d4a81abb96452c0b456
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-12-27 (Fri, 27 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix extra result register in fdiv64 lowering

There ended up being two result registers, which would fail on
select. It was really defing a new temp register in the correct def
position, instead of the correct result register.


Compare: https://github.com/llvm/llvm-project/compare/869d17d851ba...e088846712a6