[all-commits] [llvm/llvm-project] 6d88b7: [PowerPC] Modify the hasSideEffects of MTLR and MF...

[zhangkangcool via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6d88b7d6e712789115c149c5abb0f359d1222545
      https://github.com/llvm/llvm-project/commit/6d88b7d6e712789115c149c5abb0f359d1222545
  Author: Kang Zhang <shkzhang at cn.ibm.com>
  Date:   2019-12-26 (Thu, 26 Dec 2019)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/test/CodeGen/PowerPC/CSR-fit.ll
    M llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
    M llvm/test/CodeGen/PowerPC/csr-split.ll
    M llvm/test/CodeGen/PowerPC/machine-pre.ll
    M llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/pr43527.ll
    M llvm/test/CodeGen/PowerPC/pr44183.ll
    M llvm/test/CodeGen/PowerPC/sjlj.ll
    M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
    M llvm/test/CodeGen/PowerPC/sms-phi-3.ll
    M llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  Log Message:
  -----------
  [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't
have match pattern, so their hasSideEffects flag will be set true by
`llvm-tblgen`.
But in fact, we can use `[LR]` to model the two instructions, so they should not
have SideEffects.

This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D71390