[all-commits] [llvm/llvm-project] 6cba90: [AArch64][SVE] Correct intrinsics and patterns for...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cba90dc4de6427817bad763f018a502a9048f74
      https://github.com/llvm/llvm-project/commit/6cba90dc4de6427817bad763f018a502a9048f74
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2019-12-20 (Fri, 20 Dec 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-int-log-pred.ll
    M llvm/test/CodeGen/AArch64/sve-int-log.ll
    M llvm/test/CodeGen/AArch64/sve-pred-log.ll

  Log Message:
  -----------
  [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions

In general SVE intrinsics are considered predicated and merging
with everything else having suitable decoration.  For predicated
zeroing operations (like the predicate logical instructions) we
use the "_z" suffix.  After this change all intrinsics use their
expected names (i.e. orr instead of or and eor instead of xor).

I've removed intrinsics and patterns for condition code setting
instructions as that data is not returned as part of the intrinsic.
The expectation is to ask for a cc flag explicitly.

For example:
  a = and_z(pg, p1, p2)
  cc = ptest_<flag>(pg, a)

With the code generator expected to use "s" variants of instructions
when available.

Differential Revision: https://reviews.llvm.org/D71715