[all-commits] [llvm/llvm-project] acbc9a: [ARM][MVE] Fixes for tail predication.

[Sam Parker via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: acbc9aed726d4b7428691e026a214cb26ee2cf94
      https://github.com/llvm/llvm-project/commit/acbc9aed726d4b7428691e026a214cb26ee2cf94
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2019-12-20 (Fri, 20 Dec 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
    M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    A llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
    A llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
    A llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir

  Log Message:
  -----------
  [ARM][MVE] Fixes for tail predication.

1) Fix an issue with the incorrect value being used for the number of
   elements being passed to [d|w]lstp. We were trying to check that
   the value was available at LoopStart, but this doesn't consider
   that the last instruction in the block could also define the
   register. Two helpers have been added to RDA for this.
2) Insert some code to now try to move the element count def or the
   insertion point so that we can perform more tail predication.
3) Related to (1), the same off-by-one could prevent us from
   generating a low-overhead loop when a mov lr could have been
   the last instruction in the block.
4) Fix up some instruction attributes so that not all the
   low-overhead loop instructions are labelled as branches and
   terminators - as this is not true for dls/dlstp.

Differential Revision: https://reviews.llvm.org/D71609