[all-commits] [llvm/llvm-project] a116f2: [RISCV] Enable the machine outliner for RISC-V

[lewis-revill via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a116f28a0d71c221c1dc023908b180beaf22799d
      https://github.com/llvm/llvm-project/commit/a116f28a0d71c221c1dc023908b180beaf22799d
  Author: lewis-revill <lewis.revill at embecosm.com>
  Date:   2019-12-19 (Thu, 19 Dec 2019)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    A llvm/test/CodeGen/RISCV/machineoutliner.mir

  Log Message:
  -----------
  [RISCV] Enable the machine outliner for RISC-V

This patch enables the machine outliner for RISC-V and adds the
necessary logic for checking whether sequences can be safely outlined,
and describing how they should be outlined. Outlined functions are
called using the register t0 (x5) as the return address register, which
must be available for an occurrence of a sequence to be safely outlined.

Differential Revision: https://reviews.llvm.org/D66210