[all-commits] [llvm/llvm-project] bbcf1c: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce
      https://github.com/llvm/llvm-project/commit/bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce
  Author: Victor Campos <Victor.Campos at arm.com>
  Date:   2019-12-19 (Thu, 19 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    A llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

  Log Message:
  -----------
  [ARM] Improve codegen of volatile load/store of i64

Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.

These improvements cover architectures implementing ARMv5TE or Thumb-2.

Reviewers: dmgreen, efriedma, john.brawn

Reviewed By: efriedma

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70072