[all-commits] [llvm/llvm-project] 5e5e99: [AArch64] match fcvtl2 with bitcasted extract

[RotateRight via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5e5e99c041e48a69615eefd123dac23d9d0c7f73
      https://github.com/llvm/llvm-project/commit/5e5e99c041e48a69615eefd123dac23d9d0c7f73
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2019-12-18 (Wed, 18 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll

  Log Message:
  -----------
  [AArch64] match fcvtl2 with bitcasted extract

This should eliminate a regression seen in D63815.

If we are FP extending the high half extract of a vector,
we should be able to peek through a bitcast sitting
between the extract and extend.

This replaces tablegen patterns with a more general
DAG to DAG override, so we can handle any casted type.

Differential Revision: https://reviews.llvm.org/D71515