[all-commits] [llvm/llvm-project] f93387: [AArch64][SVE] Add patterns for logical immediate ...

[dancgr via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f933878991a9b00f3fcf96066678a8816da0a764
      https://github.com/llvm/llvm-project/commit/f933878991a9b00f3fcf96066678a8816da0a764
  Author: Danilo Carvalho Grael <danilo.carvalho.grael at huawei.com>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-int-log-imm.ll

  Log Message:
  -----------
  [AArch64][SVE] Add patterns for logical immediate operations.

Summary:
Add pattern matching for the following SVE logical vector and immediate instructions:
- and/bic, orr/orn, eor/eon.

Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71483