[all-commits] [llvm/llvm-project] 1274ac: [ARM][MVE] Sink vector shift operand

[Sam Parker via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1274ac3dc235dd596cc1ace2145c2b1e3c970b29
      https://github.com/llvm/llvm-project/commit/1274ac3dc235dd596cc1ace2145c2b1e3c970b29
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2019-12-12 (Thu, 12 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    A llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll
    M llvm/test/CodeGen/Thumb2/mve-shifts.ll

  Log Message:
  -----------
  [ARM][MVE] Sink vector shift operand

Recommit e0b966643fc2. sub instructions were being generated for the
negated value, and for some reason they were the register only ones.
I think the problem was because I was grabbing the 'zero' from
vmovimm, which is a target constant. Now I'm just generating a new
Constant zero and so rsb instructions are now generated.

Original commit message:

The shift amount operand can be provided in a general purpose
register so sink it. Flip the vdup and negate so the existing
patterns can be used for matching.

Differential Revision: https://reviews.llvm.org/D70841