[all-commits] [llvm/llvm-project] 65651f: [AArch64][SVE] Add DAG combine rules for gather lo...

[Andrzej Warzyński via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 65651f197a2c5a7b62f67619c169d2af616a81c6
      https://github.com/llvm/llvm-project/commit/65651f197a2c5a7b62f67619c169d2af616a81c6
  Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
  Date:   2019-12-11 (Wed, 11 Dec 2019)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

  Log Message:
  -----------
  [AArch64][SVE] Add DAG combine rules for gather loads and sext/zext

Summary:
These changes allow us to support sign-extending gather loads with the
exisiting intrinsics (i.e. @llvm.aarch64.sve.ld1.gather.*).

Reviewers: sdesmalen, huntergr, kmclaughlin, efriedma, rengolin, rovka, dancgr, mgudim

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential revision: https://reviews.llvm.org/D70812