[all-commits] [llvm/llvm-project] f008b5: [ARM] Additional tests and minor formatting. NFC

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f008b5b8ce724d60f0f0eeafceee0119c42022d4
      https://github.com/llvm/llvm-project/commit/f008b5b8ce724d60f0f0eeafceee0119c42022d4
  Author: David Green <david.green at arm.com>
  Date:   2019-12-09 (Mon, 09 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    A llvm/test/Analysis/CostModel/ARM/freeshift.ll
    A llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll

  Log Message:
  -----------
  [ARM] Additional tests and minor formatting. NFC

This adds some extra cost model tests for shifts, and does some minor
adjustments to some Neon code to make it clear as to what it applies to.
Both NFC.


  Commit: be7a1070700e591732b254e29f2dd703325fb52a
      https://github.com/llvm/llvm-project/commit/be7a1070700e591732b254e29f2dd703325fb52a
  Author: David Green <david.green at arm.com>
  Date:   2019-12-09 (Mon, 09 Dec 2019)

  Changed paths:
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/IR/Instruction.h
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
    M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
    M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
    M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Analysis/CostModel/ARM/freeshift.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll

  Log Message:
  -----------
  [ARM] Teach the Arm cost model that a Shift can be folded into other instructions

This attempts to teach the cost model in Arm that code such as:
  %s = shl i32 %a, 3
  %a = and i32 %s, %b
Can under Arm or Thumb2 become:
  and r0, r1, r2, lsl #3

So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.

We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.

Differential Revision: https://reviews.llvm.org/D70966


Compare: https://github.com/llvm/llvm-project/compare/6d5c273500ad...be7a1070700e