[all-commits] [llvm/llvm-project] 3a6eb5: [ARM] Disable VLD4 under MVE

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a6eb5f16054e8c0f41a37542a5fc806016502a0
      https://github.com/llvm/llvm-project/commit/3a6eb5f16054e8c0f41a37542a5fc806016502a0
  Author: David Green <david.green at arm.com>
  Date:   2019-12-08 (Sun, 08 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    A llvm/test/CodeGen/Thumb2/mve-vldst4.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
    A llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll

  Log Message:
  -----------
  [ARM] Disable VLD4 under MVE

Alas, using half the available vector registers in a single instruction
is just too much for the register allocator to handle. The mve-vldst4.ll
test here fails when these instructions are enabled at present. This
patch disables the generation of VLD4 and VST4 by adding a
mve-max-interleave-factor option, which we currently default to 2.

Differential Revision: https://reviews.llvm.org/D71109