[all-commits] [llvm/llvm-project] 53b95a: [AArch64][SVE] Add intrinsics and patterns for log...

[amehsan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 53b95a3cb6a7598bedbb21b2ecf742dafbd229e7
      https://github.com/llvm/llvm-project/commit/53b95a3cb6a7598bedbb21b2ecf742dafbd229e7
  Author: Danilo Carvalho Grael <danilo.carvalho.grael at huawei.com>
  Date:   2019-12-04 (Wed, 04 Dec 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-int-log-pred.ll
    M llvm/test/CodeGen/AArch64/sve-int-log.ll
    A llvm/test/CodeGen/AArch64/sve-pred-log.ll

  Log Message:
  -----------
  [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions

Add instrinics and patters for the following logical predicate instructions:
-- and, ands, bic, bics, eor, eors
-- sel
-- orr, orrs, orn, orns, nor, nors, nand, nads