[all-commits] [llvm/llvm-project] 0cc4b9: Add debug output to MipsDelaySlotFiller pass

[Alexander Richardson via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cc4b959851e7a2e98388a34e634fa922a1bc444
      https://github.com/llvm/llvm-project/commit/0cc4b959851e7a2e98388a34e634fa922a1bc444
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-04 (Wed, 04 Dec 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

  Log Message:
  -----------
  Add debug output to MipsDelaySlotFiller pass

Summary:
I was tracking down a code-generation bug in this pass and found that the
added output was useful. It is also helpful to find out why a delay slot
could not be filled even though there is clearly a valid instruction (which
appears to mostly be caused by CFI instructions).

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70940


  Commit: b91f239485fb7bb8d29be3e0b60660a2de7570a9
      https://github.com/llvm/llvm-project/commit/b91f239485fb7bb8d29be3e0b60660a2de7570a9
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-04 (Wed, 04 Dec 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
    A llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir

  Log Message:
  -----------
  MipsDelaySlotFiller: Don't move BUNDLE instructions into the delay slot

Summary:
In our CHERI fork we use BUNDLE instructions to ensure that a
three-instruction sequence to generate a program-counter-relative value is
emitted without reordering or insertions (since that would break the 32-bit
offset computation). This sequence is created in MipsExpandPseudo and we use
finalizeBundle() to create the BUNDLE instruction.

However, the delay slot filler currently breaks this pattern since the BUNDLE
will be removed and so all instructions are moved into the delay slot.
Since the delay slot only executes the first instruction, this results in
incorrect computations (and run-time crashes) if the branch is taken.

The original test cases uses CHERI instructions, so for the test case here
I simple filled a BUNDLE with a no-op DADDiu $sp_64, -16 and DADDiu $sp_64, 16.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70944


  Commit: b5f69e234ef0af43fa4b86d9977d46e0a4e442e7
      https://github.com/llvm/llvm-project/commit/b5f69e234ef0af43fa4b86d9977d46e0a4e442e7
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-04 (Wed, 04 Dec 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
    M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir

  Log Message:
  -----------
  Handle BUNDLE instructions in MipsAsmPrinter

Summary:
In our CHERI fork we use BUNDLE instructions to ensure that a
three-instruction sequence to generate a program-counter-relative value is
emitted without reordering or insertions (since that would break the 32-bit
offset computation).

Currently MipsAsmPrinter asserts when it encounters a pseudo instruction.
To handle BUNDLE we can simply skip the instruction which will then make
EmitInstruction() process the contents of the bundle in order.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70945


  Commit: 39b534da188063e9b561a272a48ecdc803d3f40e
      https://github.com/llvm/llvm-project/commit/39b534da188063e9b561a272a48ecdc803d3f40e
  Author: Alex Richardson <Alexander.Richardson at cl.cam.ac.uk>
  Date:   2019-12-04 (Wed, 04 Dec 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MipsMCInstLower.cpp
    M llvm/lib/Target/Mips/MipsMCInstLower.h

  Log Message:
  -----------
  Allow negative offsets in MipsMCInstLower::LowerOperand

Summary:
We rely on this in our CHERI backend to address the GOT by generating a
$pc-relative addresses. For this we emit the following code sequence:

lui $1, %pcrel_hi(_CHERI_CAPABILITY_TABLE_-8)
daddiu $1, $1, %pcrel_lo(_CHERI_CAPABILITY_TABLE_-4)
cgetpccincoffset $c1, $1

However, without this change the addend is implicitly converted to
UINT32_MAX and an invalid pointer value is generated.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70953


Compare: https://github.com/llvm/llvm-project/compare/ba71e84430f9...39b534da1880