[all-commits] [llvm/llvm-project] f2e7de: [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADD

[Sanne Wouda via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f2e7de81c625413a7f682c757ab64e7b63b48800
      https://github.com/llvm/llvm-project/commit/f2e7de81c625413a7f682c757ab64e7b63b48800
  Author: Sanne Wouda <Sanne.Wouda at arm.com>
  Date:   2019-12-03 (Tue, 03 Dec 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineCombinerPattern.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
    M llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll

  Log Message:
  -----------
  [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADD

Summary:
The ISel pattern for SIMD MLA is a bit too eager: it replaces the ADD with an
MLA even when the MUL cannot be eliminated, e.g. when it has another use.  An
MLA is usually has a higher latency than an ADD (and there are fewer pipes
available that can execute it), so trading an MLA for an ADD is not great.

ISel is not taking the number of uses of the MUL result into account, nor any
other factors such as the length of the critical path or other resource pressure.

The MachineCombiner is able to make these judgments so this patch ports the ISel
pattern for MUL/ADD fusing to the MachineCombiner.

Similarly for MUL/SUB -> MLS, as well as the indexed variants.

The change has no impact on SPEC CPU© intrate nor fprate.

Reviewers: dmgreen, SjoerdMeijer, fhahn, Gerolf

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70673