[all-commits] [llvm/llvm-project] 79f242: [Aarch64][SVE] Add intrinsics for gather loads (ve...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 79f2422d6a68c3fce16ed1f3111f9214169c0e1f
      https://github.com/llvm/llvm-project/commit/79f2422d6a68c3fce16ed1f3111f9214169c0e1f
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2019-12-03 (Tue, 03 Dec 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

  Log Message:
  -----------
  [Aarch64][SVE] Add intrinsics for gather loads (vector + imm)

This patch adds intrinsics for SVE gather loads from memory addresses generated by a vector base plus immediate index:
  * @llvm.aarch64.sve.ld1.gather.imm

This intrinsics maps 1-1 to the corresponding SVE instruction (example for half-words):
  * ld1h { z0.d }, p0/z, [z0.d, #16]

Committed on behalf of Andrzej Warzynski (andwar)

Reviewers: sdesmalen, huntergr, kmclaughlin, eli.friedman, rengolin, rovka, dancgr, mgudim, efriedma

Reviewed By: sdesmalen

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70806