[all-commits] [llvm/llvm-project] 63aff5: [ARM] More reversed vcmp tests. NFC

David Green via All-commits all-commits at lists.llvm.org
Mon Dec 2 11:58:32 PST 2019


  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 63aff5cd3c83cc1000cf9c85388e62071086dda2
      https://github.com/llvm/llvm-project/commit/63aff5cd3c83cc1000cf9c85388e62071086dda2
  Author: David Green <david.green at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpz.ll

  Log Message:
  -----------
  [ARM] More reversed vcmp tests. NFC


  Commit: 57d96ab593dfff39dc6eb8fa5f25eaf64af26ee1
      https://github.com/llvm/llvm-project/commit/57d96ab593dfff39dc6eb8fa5f25eaf64af26ee1
  Author: David Green <david.green at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
    M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

  Log Message:
  -----------
  [ARM] Add some VCMP folding and canonicalisation

The VCMP instructions in MVE can accept a register or ZR, but only as
the right hand operator. Most of the time this will already be correct
because the icmp will have been canonicalised that way already. There
are some cases in the lowering of float conditions that this will not
apply to though. This code should fix up those cases.

Differential Revision: https://reviews.llvm.org/D70822


  Commit: a223a4d66f4c7e28e7c6015b9e4c4a652a9677a1
      https://github.com/llvm/llvm-project/commit/a223a4d66f4c7e28e7c6015b9e4c4a652a9677a1
  Author: David Green <david.green at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMInstrNEON.td

  Log Message:
  -----------
  [ARM] Add ARMCC constants to tablegen. NFC

I got tired of looking at magic constants in tablegen files. This adds
condition codes like ARMCCeq and makes use of them.

I also removed the extra patterns for reverse condition codes from
D70296, they should now be covered by the parent commit.

Differential Revision: https://reviews.llvm.org/D70824


  Commit: 469ee617a011354b37d4c8d1c41ba8be0d719af0
      https://github.com/llvm/llvm-project/commit/469ee617a011354b37d4c8d1c41ba8be0d719af0
  Author: David Green <david.green at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td

  Log Message:
  -----------
  [ARM] Add ARMVCCThen to tablegen and make use of it. NFC

Similar to the parent, this adds some constants to tablegen to replace
the existing magic values.

Differential Revision: https://reviews.llvm.org/D70825


Compare: https://github.com/llvm/llvm-project/compare/5d0625664bf0...469ee617a011


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