[all-commits] [llvm/llvm-project] 01aefa: [ARM, MVE] Add an InstCombine rule permitting VPNOT.

[Simon Tatham via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 01aefae4a173c32a0235feb9600beffbcd0308b4
      https://github.com/llvm/llvm-project/commit/01aefae4a173c32a0235feb9600beffbcd0308b4
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll
    M llvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll

  Log Message:
  -----------
  [ARM,MVE] Add an InstCombine rule permitting VPNOT.

Summary:
If a user writing C code using the ACLE MVE intrinsics generates a
predicate and then complements it, then the resulting IR will use the
`pred_v2i` IR intrinsic to turn some `<n x i1>` vector into a 16-bit
integer; complement that integer; and convert back. This will generate
machine code that moves the predicate out of the `P0` register,
complements it in an integer GPR, and moves it back in again.

This InstCombine rule replaces `i2v(~v2i(x))` with a direct complement
of the original predicate vector, which we can already instruction-
select as the VPNOT instruction which complements P0 in place.

Reviewers: ostannard, MarkMurrayARM, dmgreen

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70484


  Commit: 48cce077efcc3c3637aac0143b3c2c9d1cf7ab8b
      https://github.com/llvm/llvm-project/commit/48cce077efcc3c3637aac0143b3c2c9d1cf7ab8b
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/MVETailPredication.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-widen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
    M llvm/test/CodeGen/Thumb2/mve-vctp.ll
    M llvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll

  Log Message:
  -----------
  [ARM,MVE] Rename and clean up VCTP IR intrinsics.

Summary:
D65884 added a set of Arm IR intrinsics for the MVE VCTP instruction,
to use in tail predication. But the 64-bit one doesn't work properly:
its predicate type is `<2 x i1>` / `v2i1`, which isn't a legal MVE
type (due to not having a full set of instructions that manipulate it
usefully). The test of `vctp64` in `basic-tail-pred.ll` goes through
`opt` fine, as the test expects, but if you then feed it to `llc` it
causes a type legality failure at isel time.

The usual workaround we've been using in the rest of the MVE
intrinsics family is to bodge `v2i1` into `v4i1`. So I've adjusted the
`vctp64` IR intrinsic to do that, and completely removed the code (and
test) that uses that intrinsic for 64-bit tail predication. That will
allow me to add isel rules (upcoming in D70485) that actually generate
the VCTP64 instruction.

Also renamed all four of these IR intrinsics so that they have `mve`
in the name, since its absence was confusing.

Reviewers: ostannard, MarkMurrayARM, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: samparker, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70592


  Commit: d173fb5d2854a1ce42bcc34832db5039b2c60e69
      https://github.com/llvm/llvm-project/commit/d173fb5d2854a1ce42bcc34832db5039b2c60e69
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2019-12-02 (Mon, 02 Dec 2019)

  Changed paths:
    M clang/include/clang/Basic/arm_mve.td
    A clang/test/CodeGen/arm-mve-intrinsics/predicates.c
    M clang/utils/TableGen/MveEmitter.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    A llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll

  Log Message:
  -----------
  [ARM,MVE] Add intrinsics to deal with predicates.

Summary:
This commit adds the `vpselq` intrinsics which take an MVE predicate
word and select lanes from two vectors; the `vctp` intrinsics which
create a tail predicate word suitable for processing the first m
elements of a vector (e.g. in the last iteration of a loop); and
`vpnot`, which simply complements a predicate word and is just
syntactic sugar for the `~` operator.

The `vctp` ACLE intrinsics are lowered to the IR intrinsics we've
already added (and which D70592 just reorganized). I've filled in the
missing isel rule for VCTP64, and added another set of rules to
generate the predicated forms.

I needed one small tweak in MveEmitter to allow the `unpromoted` type
modifier to apply to predicates as well as integers, so that `vpnot`
doesn't pointlessly convert its input integer to an `<n x i1>` before
complementing it.

Reviewers: ostannard, MarkMurrayARM, dmgreen

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70485


Compare: https://github.com/llvm/llvm-project/compare/effcdc3a82f2...d173fb5d2854