[all-commits] [llvm/llvm-project] 549db7: [ARM] Lots of MVE offset masked load and store tes...

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 549db744bde29c8331411a4b41607a33c363c108
      https://github.com/llvm/llvm-project/commit/549db744bde29c8331411a4b41607a33c363c108
  Author: David Green <david.green at arm.com>
  Date:   2019-11-26 (Tue, 26 Nov 2019)

  Changed paths:
    A llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll
    A llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll
    A llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

  Log Message:
  -----------
  [ARM] Lots of MVE offset masked load and store tests. NFC


  Commit: b5315ae8ffa6fb8befdd558d0dfd04295dbc5523
      https://github.com/llvm/llvm-project/commit/b5315ae8ffa6fb8befdd558d0dfd04295dbc5523
  Author: David Green <david.green at arm.com>
  Date:   2019-11-26 (Tue, 26 Nov 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-load.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-store.ll

  Log Message:
  -----------
  [Codegen][ARM] Add addressing modes from masked loads and stores

MVE has a basic symmetry between it's normal loads/store operations and
the masked variants. This means that masked loads and stores can use
pre-inc and post-inc addressing modes, just like the standard loads and
stores already do.

To enable that, this patch adds all the relevant infrastructure for
treating masked loads/stores addressing modes in the same way as normal
loads/stores.

This involves:
- Adding an AddressingMode to MaskedLoadStoreSDNode, along with an extra
   Offset operand that is added after the PtrBase.
- Extending the IndexedModeActions from 8bits to 16bits to store the
   legality of masked operations as well as normal ones. This array is
   fairly small, so doubling the size still won't make it very large.
   Offset masked loads can then be controlled with
   setIndexedMaskedLoadAction, similar to standard loads.
- The same methods that combine to indexed loads, such as
   CombineToPostIndexedLoadStore, are adjusted to handle masked loads in
   the same way.
- The ARM backend is then adjusted to make use of these indexed masked
   loads/stores.
- The X86 backend is adjusted to hopefully be no functional changes.

Differential Revision: https://reviews.llvm.org/D70176


  Commit: 4965779f171343fc7e74276a548ec30906a740d0
      https://github.com/llvm/llvm-project/commit/4965779f171343fc7e74276a548ec30906a740d0
  Author: David Green <david.green at arm.com>
  Date:   2019-11-26 (Tue, 26 Nov 2019)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrMVE.td

  Log Message:
  -----------
  [ARM] Clean up the load and store code. NFC

Some of these patterns have grown quite organically. I've tried to
organise them a little here, moving all the PatFlags together and giving
them a more consistent naming scheme, to allow some of the later
patterns to be merged into a single multiclass.

Differential Revision: https://reviews.llvm.org/D70178


Compare: https://github.com/llvm/llvm-project/compare/184d72a7c6a7...4965779f1713