[all-commits] [llvm/llvm-project] 48b7fe: [AArch64] Add the pipeline model for Exynos M5

[Evandro Menezes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 48b7fe02a1147a734ba8b28f53b4b7ede30d0843
      https://github.com/llvm/llvm-project/commit/48b7fe02a1147a734ba8b28f53b4b7ede30d0843
  Author: Evandro Menezes <e.menezes at samsung.com>
  Date:   2019-11-22 (Fri, 22 Nov 2019)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    A llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    A llvm/test/tools/llvm-mca/AArch64/Exynos/aes.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld1.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld2.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld3.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld4.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st1.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st2.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st3.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st4.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/crc.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/divide-multiply.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/double-recp.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/double-rsqrt.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/double-sqrt.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-divide-multiply.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-integer.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-load.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-recp.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-rsqrt.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-sqrt.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/float-store.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/load.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s
    A llvm/test/tools/llvm-mca/AArch64/Exynos/store.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/zero-latency-move.s

  Log Message:
  -----------
  [AArch64] Add the pipeline model for Exynos M5

Add the scheduling and cost models for Exynos M5.