[all-commits] [llvm/llvm-project] 714aab: Temporarily Revert "[SLP] allow forming 2-way redu...

[Eric Christopher via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 714aabacfb0f9b372cf230f1b7113e3ebd0e661d
      https://github.com/llvm/llvm-project/commit/714aabacfb0f9b372cf230f1b7113e3ebd0e661d
  Author: Eric Christopher <echristo at gmail.com>
  Date:   2019-11-20 (Wed, 20 Nov 2019)

  Changed paths:
    M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Feature/weak_constant.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll

  Log Message:
  -----------
  Temporarily Revert "[SLP] allow forming 2-way reduction patterns" and update testcases.

After speaking with Sanjay - seeing a number of miscompiles and working
on tracking down a testcase. None of the follow on patches seem to
have helped so far.

This reverts commit 8a0aa5310bccbb42d16d11db090419fcefdd1376.


  Commit: 8259182e51ccf23c13d670f6f0401ce33f6c742f
      https://github.com/llvm/llvm-project/commit/8259182e51ccf23c13d670f6f0401ce33f6c742f
  Author: Eric Christopher <echristo at gmail.com>
  Date:   2019-11-20 (Wed, 20 Nov 2019)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    R llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    R llvm/test/tools/llvm-mca/AArch64/Exynos/aes.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld1.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld2.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld3.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld4.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st1.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st2.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st3.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-st4.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/crc.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/divide-multiply.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/double-recp.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/double-rsqrt.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/double-sqrt.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-divide-multiply.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-integer.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-load.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-recp.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-rsqrt.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-sqrt.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/float-store.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/load.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s
    R llvm/test/tools/llvm-mca/AArch64/Exynos/store.s
    M llvm/test/tools/llvm-mca/AArch64/Exynos/zero-latency-move.s

  Log Message:
  -----------
  Revert "[AArch64] Add the pipeline model for Exynos M5"
as it's causing test failures in llvm-mca.

This reverts commit 9bdfee2a3bd13d405ce1592930182f23849d2897.


Compare: https://github.com/llvm/llvm-project/compare/8a0aa5310bcc...8259182e51cc