[all-commits] [llvm/llvm-project] 0a58ef: [Hexagon] Require PS_aligna whenever variable-size...

[Krzysztof Parzyszek via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a58ef5eb5e1a243756f649f82834281ac3dd7ff
      https://github.com/llvm/llvm-project/commit/0a58ef5eb5e1a243756f649f82834281ac3dd7ff
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2019-11-12 (Tue, 12 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

  Log Message:
  -----------
  [Hexagon] Require PS_aligna whenever variable-sized objects are present


  Commit: 67294c97fbfde6541b5f89d9d83c7fcba31c5f3b
      https://github.com/llvm/llvm-project/commit/67294c97fbfde6541b5f89d9d83c7fcba31c5f3b
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2019-11-12 (Tue, 12 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonVExtract.cpp

  Log Message:
  -----------
  [Hexagon] Handle stack realignment in hexagon-vextract


  Commit: e3eb10c5419d89171bc97ca21aba7c381827c45e
      https://github.com/llvm/llvm-project/commit/e3eb10c5419d89171bc97ca21aba7c381827c45e
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2019-11-12 (Tue, 12 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

  Log Message:
  -----------
  [Hexagon] Convert stack object offsets to int64, NFC

This will print [SP-56] instead of [SP+4294967240].


  Commit: 592dd459242946593920911936aea47461e0faaa
      https://github.com/llvm/llvm-project/commit/592dd459242946593920911936aea47461e0faaa
  Author: Krzysztof Parzyszek <kparzysz at quicinc.com>
  Date:   2019-11-12 (Tue, 12 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonPseudo.td
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    A llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
    M llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll

  Log Message:
  -----------
  [Hexagon] Fix vector spill expansion to use proper alignment

1. Add pseudos PS_vloadrv_ai and PS_vstorerv_ai: those are now used
   for single vector registers in loadRegFromStackSlot (and store...).
2. Remove pseudos PS_vloadrwu_ai and PS_vstorerwu_ai. The alignment is
   now checked when expanding spill pseudos (both in frame lowering
   and in expand-post-ra-pseudos), and a proper instruction is generated.
3. Update MachineMemOperands when dealigning vector spill slots.
4. Return vector predicate registers in getCallerSavedRegs.


Compare: https://github.com/llvm/llvm-project/compare/228dd96c6fdd...592dd4592429