[all-commits] [llvm/llvm-project] 7bed38: [mips] Implement Octeon+ `saa` and `saad` instruct...

[Simon Atanasyan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7bed381eae12277d6e0ef7e8a56491d11589ee7f
      https://github.com/llvm/llvm-project/commit/7bed381eae12277d6e0ef7e8a56491d11589ee7f
  Author: Simon Atanasyan <simon at atanasyan.com>
  Date:   2019-11-07 (Thu, 07 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
    M llvm/lib/Target/Mips/Mips.td
    M llvm/lib/Target/Mips/Mips64InstrInfo.td
    M llvm/lib/Target/Mips/MipsInstrFormats.td
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/lib/Target/Mips/MipsScheduleGeneric.td
    M llvm/lib/Target/Mips/MipsScheduleP5600.td
    M llvm/lib/Target/Mips/MipsSubtarget.cpp
    M llvm/lib/Target/Mips/MipsSubtarget.h
    A llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt
    A llvm/test/MC/Disassembler/Mips/octeonp/valid.txt
    A llvm/test/MC/Mips/cnmipsp/invalid.s
    A llvm/test/MC/Mips/cnmipsp/valid.s
    M llvm/test/MC/Mips/elf_eflags.s
    M llvm/test/MC/Mips/elf_header.s
    A llvm/test/MC/Mips/macro-saa.s
    A llvm/test/MC/Mips/macro-saad.s

  Log Message:
  -----------
  [mips] Implement Octeon+ `saa` and `saad` instructions

`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

   memory[base] = memory[base] + rt

These instructions are available for "Octeon+" CPU. The patch adds support
for both instructions to MIPS assembler and diassembler and introduces new
CPU type - "octeon+".

Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP`
ISA extension flag support.

Differential Revision: https://reviews.llvm.org/D69849


  Commit: 3718102d40d60ba415ac2b2b1108e411838838a5
      https://github.com/llvm/llvm-project/commit/3718102d40d60ba415ac2b2b1108e411838838a5
  Author: Simon Atanasyan <simon at atanasyan.com>
  Date:   2019-11-07 (Thu, 07 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    M llvm/test/MC/Mips/set-arch.s

  Log Message:
  -----------
  [mips] Support `octeon+` CPU in the `.set arch=` directive

Differential Revision: https://reviews.llvm.org/D69850


  Commit: bf996f761b99108c71efc84688597b7c3c63139e
      https://github.com/llvm/llvm-project/commit/bf996f761b99108c71efc84688597b7c3c63139e
  Author: Simon Atanasyan <simon at atanasyan.com>
  Date:   2019-11-07 (Thu, 07 Nov 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
    M llvm/test/MC/Mips/mips_abi_flags_xx.s

  Log Message:
  -----------
  [mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` section

Differential Revision: https://reviews.llvm.org/D69851


  Commit: 3552d3e0f7c943c3547c0227ddd80fd4d0732a7e
      https://github.com/llvm/llvm-project/commit/3552d3e0f7c943c3547c0227ddd80fd4d0732a7e
  Author: Simon Atanasyan <simon at atanasyan.com>
  Date:   2019-11-07 (Thu, 07 Nov 2019)

  Changed paths:
    M clang/lib/Basic/Targets/Mips.cpp
    M clang/lib/Basic/Targets/Mips.h
    M clang/lib/Driver/ToolChains/Gnu.cpp
    M clang/test/Driver/mips-abi.c
    M clang/test/Driver/mips-as.c
    M clang/test/Misc/target-invalid-cpu-note.c

  Log Message:
  -----------
  [mips] Add `octeon+` to the list of CPUs accepted by the driver


  Commit: a751f557d824c569a96051ea5feef1ff32bb4723
      https://github.com/llvm/llvm-project/commit/a751f557d824c569a96051ea5feef1ff32bb4723
  Author: Simon Atanasyan <simon at atanasyan.com>
  Date:   2019-11-07 (Thu, 07 Nov 2019)

  Changed paths:
    M clang/lib/Basic/Targets/Mips.cpp
    M clang/test/Preprocessor/init.c

  Log Message:
  -----------
  [mips] Set macros for Octeon+ CPU


Compare: https://github.com/llvm/llvm-project/compare/eaff3004019f...a751f557d824