[all-commits] [llvm/llvm-project] e74c5b: [globalisel] Rename G_GEP to G_PTR_ADD

Daniel Sanders via All-commits all-commits at lists.llvm.org
Tue Nov 5 10:31:28 PST 2019 

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e74c5b96610dfb03825d31035f50813af58beac5
      https://github.com/llvm/llvm-project/commit/e74c5b96610dfb03825d31035f50813af58beac5
  Author: Daniel Sanders <daniel_l_sanders at apple.com>
  Date:   2019-11-05 (Tue, 05 Nov 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/AArch64/AArch64CallLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/ARM/ARMCallLowering.cpp
    M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
    M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
    M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
    M llvm/lib/Target/Mips/MipsCallLowering.cpp
    M llvm/lib/Target/Mips/MipsInstructionSelector.cpp
    M llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
    M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
    M llvm/lib/Target/X86/X86CallLowering.cpp
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/lib/Target/X86/X86LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
    R llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
    R llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    R llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-gep.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
    R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-gep.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
    M llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
    M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
    M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
    R llvm/test/CodeGen/X86/GlobalISel/gep.ll
    M llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
    R llvm/test/CodeGen/X86/GlobalISel/legalize-gep.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
    A llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
    A llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
    R llvm/test/CodeGen/X86/GlobalISel/select-gep.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
    A llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
    R llvm/test/MachineVerifier/test_g_gep.mir
    A llvm/test/MachineVerifier/test_g_ptr_add.mir

  Log Message:
  -----------
  [globalisel] Rename G_GEP to G_PTR_ADD

Summary:
G_GEP is rather poorly named. It's a simple pointer+scalar addition and
doesn't support any of the complexities of getelementptr. I therefore
propose that we rename it. There's a G_PTR_MASK so let's follow that
convention and go with G_PTR_ADD

Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm

Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69734

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