[all-commits] [llvm/llvm-project] 0d47c7: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjo...

[Luís Marques via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d47c7aba364962d14e4e25249d75da7bdf29b78
      https://github.com/llvm/llvm-project/commit/0d47c7aba364962d14e4e25249d75da7bdf29b78
  Author: Luís Marques <luismarques at lowrisc.org>
  Date:   2019-11-05 (Tue, 05 Nov 2019)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    A llvm/test/CodeGen/RISCV/disjoint.ll

  Log Message:
  -----------
  [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook

Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint`
hook. The test could check for instruction reorderings, but to avoid
being brittle it just checks instruction dependencies.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67046