[all-commits] [llvm/llvm-project] 51b4b1: [RISCV] Implement the TargetLowering::getRegisterB...

[Luís Marques via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 51b4b17eb7e6ee2312e3230c7e097df501006360
      https://github.com/llvm/llvm-project/commit/51b4b17eb7e6ee2312e3230c7e097df501006360
  Author: Luís Marques <luismarques at lowrisc.org>
  Date:   2019-11-04 (Mon, 04 Nov 2019)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    A llvm/test/CodeGen/RISCV/get-register-invalid.ll
    A llvm/test/CodeGen/RISCV/get-register-noreserve.ll
    A llvm/test/CodeGen/RISCV/get-register-reserve.ll

  Log Message:
  -----------
  [RISCV] Implement the TargetLowering::getRegisterByName hook

Summary: The hook should work for any RISC-V register. Non-allocatable registers
do not need to be reserved, for the remaining the hook will only succeed
if you pass clang the -ffixed-xX flag. This builds upon D67185, which
currently only allows reserving GPRs.

Reviewers: asb, lenary

Reviewed By: lenary

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69130