[all-commits] [llvm/llvm-project] ed7bcb: [AArch64][SVE] Add patterns for some integer vecto...

[amehsan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ed7bcb2cb1575d26bd9161103fae01d1a5fa4b07
      https://github.com/llvm/llvm-project/commit/ed7bcb2cb1575d26bd9161103fae01d1a5fa4b07
  Author: Ehsan Amiri <ehsanamiri at gmail.com>
  Date:   2019-10-30 (Wed, 30 Oct 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-int-arith-pred.ll
    A llvm/test/CodeGen/AArch64/sve-int-arith.ll
    A llvm/test/CodeGen/AArch64/sve-int-log.ll

  Log Message:
  -----------
  [AArch64][SVE] Add patterns for some integer vector instructions

Add pattern matching for SVE vector instructions:

-- add, sub, and, or, xor instructions
-- sqadd, uqadd, sqsub, uqsub target-independent intrinsics
-- bic intrinsics
-- predicated add, sub, subr intrinsics

Patch Review: https://reviews.llvm.org/D69128
Patch authored by: dancgr (Danilo Carvalho Grael)