[all-commits] [llvm/llvm-project] 8f48ba: [X86] Model MXCSR for all SSE instructions

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f48ba993ba32925f37a374f624663da37d96254
      https://github.com/llvm/llvm-project/commit/8f48ba993ba32925f37a374f624663da37d96254
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2019-10-30 (Wed, 30 Oct 2019)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrFormats.td
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/test/CodeGen/MIR/X86/constant-pool.mir
    M llvm/test/CodeGen/MIR/X86/fastmath.mir
    M llvm/test/CodeGen/MIR/X86/memory-operands.mir
    M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
    M llvm/test/CodeGen/X86/ipra-reg-usage.ll

  Log Message:
  -----------
  [X86] Model MXCSR for all SSE instructions

This patch adds MXCSR as a reserved physical register and models its use
by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the
instructions that possibly can raise FP exception according to the
architecture definition.

Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled. *Changes* of the MXCSR
due to exceptions are not modeled.

Patch by Pengfei Wang

Differential Revision: https://reviews.llvm.org/D68121