[all-commits] [llvm/llvm-project] d9e0a2: AMDGPU: Disallow spill folding with m0 copies

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d9e0a2942ac71327166a3a597e8383192fd19b17
      https://github.com/llvm/llvm-project/commit/d9e0a2942ac71327166a3a597e8383192fd19b17
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-10-30 (Wed, 30 Oct 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    A llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir

  Log Message:
  -----------
  AMDGPU: Disallow spill folding with m0 copies

readlane and writelane instructions are not allowed to use m0 as the
data operand, so spilling them is tricky and would require an
intermediate SGPR to spill it. Constrain the virtual register class in
this caes to disallow the inline spiller from folding the m0 operand
directly into the spill instruction.

I copied this hack from AArch64 which has the same problem for $sp.