[all-commits] [llvm/llvm-project] f15cf9: [PowerPC] Clear the sideeffect bit for those instr...

[QingShan Zhang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f15cf93899df3e8863207b40c3900facb0ccc356
      https://github.com/llvm/llvm-project/commit/f15cf93899df3e8863207b40c3900facb0ccc356
  Author: QingShan Zhang <48825004 at qq.com>
  Date:   2019-10-30 (Wed, 30 Oct 2019)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/test/CodeGen/PowerPC/extract-and-store.ll
    M llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll

  Log Message:
  -----------
  [PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern

If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well.
If not, the tblgen will set it as true that hurt the scheduling.

PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according
to the register pressure. We need to clear the sideeffect flag for these instructions.

Differential Revision: https://reviews.llvm.org/D69232