[all-commits] [llvm/llvm-project] 1e9de0: [SVE][AArch64] Adding pattern matching for some SV...

[amehsan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e9de0215f0488bae6c2a7cc0c9c4324d981ad30
      https://github.com/llvm/llvm-project/commit/1e9de0215f0488bae6c2a7cc0c9c4324d981ad30
  Author: Ehsan Amiri <ehsanamiri at gmail.com>
  Date:   2019-10-29 (Tue, 29 Oct 2019)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-fp.ll

  Log Message:
  -----------
  [SVE][AArch64] Adding pattern matching for some SVE instructions.

Adding patten matching for two SVE intrinsics: frecps and frsqrts.
Also added patterns for fsub and fmul - these SDNodes directly correspond
to machine instructions.

Review: https://reviews.llvm.org/D68476
Patch authored by mgudim (Mikhail Gudim).