[all-commits] [llvm/llvm-project] da720a: [AArch64][SVE] Implement masked load intrinsics

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: da720a38b9f24cc92b46fd5df503b13d5c823285
      https://github.com/llvm/llvm-project/commit/da720a38b9f24cc92b46fd5df503b13d5c823285
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
    A llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
    A llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll

  Log Message:
  -----------
  [AArch64][SVE] Implement masked load intrinsics

Summary:
Adds support for codegen of masked loads, with non-extending,
zero-extending and sign-extending variants.

Reviewers: huntergr, rovka, greened, dmgreen

Reviewed By: dmgreen

Subscribers: dmgreen, samparker, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68877