[all-commits] [llvm/llvm-project] aed9d6: [RISCV] Add support for -ffixed-xX flags
Simon Cook via All-commits
all-commits at lists.llvm.org
Tue Oct 22 13:29:37 PDT 2019
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: aed9d6d64a38d155cd09232da5640b5ade069bd9
https://github.com/llvm/llvm-project/commit/aed9d6d64a38d155cd09232da5640b5ade069bd9
Author: Simon Cook <simon.cook at embecosm.com>
Date: 2019-10-22 (Tue, 22 Oct 2019)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
A clang/test/Driver/riscv-fixed-x-register.c
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
A llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
A llvm/test/CodeGen/RISCV/reserved-regs.ll
Log Message:
-----------
[RISCV] Add support for -ffixed-xX flags
This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. The backend checks that it does not need to write to
any reserved register; if it does a relevant error is generated.
Differential Revision: https://reviews.llvm.org/D67185
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