[all-commits] [llvm/llvm-project] 8ebbf2: AMDGPU: Erase redundant redefs of m0 in SIFoldOper...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ebbf25cb1e9b2c95903917b2aa72363e5b20a42
      https://github.com/llvm/llvm-project/commit/8ebbf25cb1e9b2c95903917b2aa72363e5b20a42
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-10-21 (Mon, 21 Oct 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    A llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir

  Log Message:
  -----------
  AMDGPU: Erase redundant redefs of m0 in SIFoldOperands

Only handle simple inter-block redefs of m0 to the same value. This
avoids interference from redefs of m0 in SILoadStoreOptimzer. I was
initially teaching that pass to ignore redefs of m0, but having them
not exist beforehand is much simpler.

This is in preparation for deleting the current special m0 handling in
SIFixSGPRCopies to allow the register coalescer to handle the
difficult cases.

llvm-svn: 375449


  Commit: 38038f116f7b948a700e0edc4d3687c7b7fda926
      https://github.com/llvm/llvm-project/commit/38038f116f7b948a700e0edc4d3687c7b7fda926
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2019-10-21 (Mon, 21 Oct 2019)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll

  Log Message:
  -----------
  AMDGPU: Use CopyToReg for interp intrinsic lowering

This doesn't use the default value, so doesn't benefit from the hack
to help optimize it.

llvm-svn: 375450


Compare: https://github.com/llvm/llvm-project/compare/dd6cf159bab7...38038f116f7b