[www-scripts] Clang Attribute Doc Update: SUCCESS

LLVM via www-scripts www-scripts at lists.llvm.org
Tue Dec 12 03:01:33 PST 2017 

UPDATING /opt/clang_commandline_docs//src/llvm LLVM SOURCES
Updating '.':
U    unittests/ADT/TinyPtrVectorTest.cpp
U    lib/CodeGen/MacroFusion.cpp
U    lib/CodeGen/GlobalISel/IRTranslator.cpp
U    lib/CodeGen/SelectionDAG/DAGCombiner.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/IR/SafepointIRVerifier.cpp
U    lib/Analysis/InstructionSimplify.cpp
U    lib/Target/X86/X86ScheduleZnver1.td
U    lib/Target/X86/X86SchedSkylakeClient.td
U    lib/Target/X86/X86InstrFMA.td
U    lib/Target/X86/X86InstrXOP.td
U    lib/Target/X86/X86InstrExtension.td
U    lib/Target/X86/X86SchedSkylakeServer.td
U    lib/Target/X86/X86InstrAVX512.td
U    lib/Target/X86/X86SchedHaswell.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86SchedBroadwell.td
U    lib/Target/RISCV/RISCVInstrInfo.td
U    lib/Target/RISCV/RISCVRegisterInfo.cpp
U    lib/Target/RISCV/RISCVFrameLowering.cpp
U    lib/Target/RISCV/RISCVISelLowering.cpp
U    lib/Target/RISCV/RISCVCallingConv.td
U    lib/Target/RISCV/CMakeLists.txt
U    lib/Target/RISCV/RISCVISelDAGToDAG.cpp
U    lib/Target/RISCV/RISCVFrameLowering.h
U    lib/Target/RISCV/RISCVISelLowering.h
U    lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
U    lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
U    lib/Target/Hexagon/HexagonISelLowering.h
U    lib/Target/Hexagon/HexagonIntrinsics.td
U    lib/Target/Hexagon/HexagonIICHVX.td
U    lib/Target/Hexagon/HexagonInstrFormats.td
U    lib/Target/Hexagon/HexagonRegisterInfo.td
U    lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
U    lib/Target/Hexagon/HexagonDepInstrInfo.td
U    lib/Target/Hexagon/HexagonISelDAGToDAG.h
U    lib/Target/Hexagon/HexagonISelLowering.cpp
U    lib/Target/Hexagon/HexagonDepTimingClasses.h
U    lib/Target/Hexagon/Hexagon.td
U    lib/Target/Hexagon/HexagonDepIICHVX.td
U    lib/Target/Hexagon/HexagonDepIICScalar.td
U    lib/Target/Hexagon/HexagonDepArch.h
U    lib/Target/Hexagon/HexagonDepITypes.h
U    lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
U    lib/Target/Hexagon/HexagonInstrInfo.h
A    lib/Target/Hexagon/HexagonInstrFormatsV65.td
A    lib/Target/Hexagon/HexagonPatternsV65.td
U    lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
U    lib/Target/Hexagon/HexagonDepMappings.td
U    lib/Target/Hexagon/HexagonSubtarget.cpp
U    lib/Target/Hexagon/HexagonFrameLowering.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
U    lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
U    lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
U    lib/Target/Sparc/SparcInstrVIS.td
U    lib/Target/Sparc/SparcISelLowering.h
U    lib/Target/Sparc/SparcISelLowering.cpp
D    lib/Target/Mips/MicroMips64r6InstrFormats.td
D    lib/Target/Mips/MicroMips64r6InstrInfo.td
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
U    lib/Target/Hexagon/HexagonSchedule.td
A    lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td
U    lib/Target/Hexagon/HexagonRegisterInfo.cpp
U    lib/Target/Hexagon/HexagonDepInstrFormats.td
A    lib/Target/Hexagon/HexagonDepDecoders.h
U    lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
U    lib/Target/Mips/MipsRegisterInfo.cpp
U    lib/Target/Mips/MicroMipsInstrInfo.td
U    lib/Target/Mips/Relocation.txt
U    lib/Target/Mips/MicroMips32r6InstrFormats.td
U    lib/Target/Mips/MipsISelLowering.cpp
U    lib/Target/Mips/AsmParser/MipsAsmParser.cpp
U    lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
U    lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
U    lib/Transforms/InstCombine/InstCombineVectorOps.cpp
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
U    lib/Target/Hexagon/HexagonInstrInfo.cpp
U    lib/Target/Hexagon/CMakeLists.txt
U    lib/Target/Hexagon/HexagonDepOperands.td
U    lib/Target/Hexagon/HexagonVLIWPacketizer.h
U    lib/Target/Hexagon/HexagonAsmPrinter.cpp
U    lib/Target/Hexagon/HexagonDepITypes.td
U    lib/Target/Mips/MipsScheduleP5600.td
U    lib/Target/Mips/MicroMipsSizeReduction.cpp
U    lib/Target/Mips/Disassembler/MipsDisassembler.cpp
U    lib/Target/Mips/Mips64InstrInfo.td
U    lib/Target/Mips/MipsInstrInfo.td
U    lib/Target/Mips/Mips64r6InstrInfo.td
U    lib/Target/AMDGPU/SIRegisterInfo.cpp
U    lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
U    lib/Target/AMDGPU/SIRegisterInfo.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
U    lib/Target/Hexagon/HexagonTargetMachine.cpp
U    lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
A    lib/Target/Hexagon/HexagonScheduleV65.td
U    lib/Target/Hexagon/HexagonSubtarget.h
A    lib/Target/Hexagon/HexagonGatherPacketize.cpp
U    lib/Target/Hexagon/HexagonDepArch.td
U    lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
U    lib/Target/Mips/MipsMachineFunction.cpp
U    lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
U    lib/Target/Mips/MipsSubtarget.h
U    lib/Target/Mips/MipsSubtarget.cpp
U    lib/Target/Mips/MipsInstrInfo.cpp
U    lib/Target/Mips/MipsRegisterInfo.td
U    lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
U    lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
U    lib/Target/AMDGPU/SIDefines.h
U    lib/Target/PowerPC/PPCISelLowering.cpp
U    lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
U    lib/Target/PowerPC/PPCExpandISEL.cpp
U    lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
U    lib/Target/ARM/ARMISelLowering.cpp
D    test/Transforms/InstCombine/pr28725.ll
U    test/Transforms/InstCombine/vector_insertelt_shuffle.ll
U    test/Transforms/InstCombine/out-of-bounds-indexes.ll
D    test/Transforms/InstSimplify/insertelement.ll
U    test/Transforms/InstSimplify/pr28725.ll
D    test/MC/Mips/micromips64r6
D    test/MC/Disassembler/Mips/micromips64r6
U    test/CodeGen/SPARC/float.ll
D    test/CodeGen/Mips/cannot-copy-registers.ll
U    lib/Transforms/Instrumentation/MemorySanitizer.cpp
U    lib/MC/WasmObjectWriter.cpp
U    test/tools/llvm-cov/showLineExecutionCounts.cpp
U    lib/Transforms/Scalar/LoopStrengthReduce.cpp
U    lib/Transforms/Vectorize/LoopVectorize.cpp
U    lib/DebugInfo/DWARF/DWARFVerifier.cpp
U    lib/Transforms/Scalar/CallSiteSplitting.cpp
U    lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
U    test/DebugInfo/dwarfdump-accel.test
U    lib/Transforms/Instrumentation/AddressSanitizer.cpp
U    lib/DebugInfo/DWARF/DWARFContext.cpp
U    test/DebugInfo/Inputs/dwarfdump-objc.x86_64.o
A    test/Transforms/CallSiteSplitting/callsite-split-debug.ll
U    test/MC/Hexagon/v60-misc.s
U    test/MC/Hexagon/new-value-check.s
A    test/MC/Mips/micromips64r6-unsupported.s
U    test/MC/WebAssembly/func-address.ll
U    test/MC/WebAssembly/external-func-address.ll
U    test/MC/AMDGPU/trap.s
A    test/Instrumentation/AddressSanitizer/local_stack_base.ll
U    test/MC/AVR/symbol_relocation.s
A    test/MC/Hexagon/v65_all.s
U    test/MC/Hexagon/PacketRules/endloop_branches.s
U    test/MC/WebAssembly/reloc-data.ll
U    test/MC/WebAssembly/weak.ll
U    test/MC/AMDGPU/literalv216-err.s
A    test/MC/Disassembler/AMDGPU/trap_gfx9.txt
U    test/Instrumentation/AddressSanitizer/debug_info.ll
U    test/CodeGen/Mips/llvm-ir/srem.ll
A    test/Transforms/LoopVectorize/X86/reduction-small-size.ll
A    test/MC/Hexagon/vtmp_def.s
A    test/MC/Hexagon/hvx-double-implies-hvx.s
U    test/MC/Mips/mips64extins.s
U    test/MC/WebAssembly/weak-alias.ll
U    test/MC/WebAssembly/init-fini-array.ll
U    test/MC/AMDGPU/vop_sdwa.s
U    test/Instrumentation/AddressSanitizer/basic.ll
U    test/CodeGen/Mips/tailcall/tailcall.ll
A    test/CodeGen/ARM/pr34045-2.ll
A    test/CodeGen/ARM/pr34045.ll
U    test/CodeGen/ARM/intrinsics-overflow.ll
U    test/CodeGen/Mips/llvm-ir/xor.ll
U    test/CodeGen/Mips/llvm-ir/add.ll
U    test/CodeGen/Mips/llvm-ir/and.ll
U    test/CodeGen/Mips/fcmp.ll
U    test/CodeGen/Mips/mips64shift.ll
A    test/CodeGen/PowerPC/expand-isel-9.mir
U    test/DebugInfo/Generic/block-asan.ll
U    test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll
U    test/MC/AVR/relocations.s
A    test/MC/Hexagon/vscatter-slot.s
A    test/MC/Hexagon/vpred_defs.s
U    test/MC/WebAssembly/reloc-code.ll
U    test/MC/WebAssembly/sections.ll
U    test/MC/AMDGPU/vop1-gfx9-err.s
U    test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
U    test/Instrumentation/AddressSanitizer/stack_layout.ll
U    test/CodeGen/Mips/llvm-ir/udiv.ll
U    test/CodeGen/Mips/llvm-ir/or.ll
U    test/CodeGen/Mips/llvm-ir/not.ll
U    test/CodeGen/Mips/lw16-base-reg.ll
A    test/CodeGen/Mips/micromips64r6-unsupported.ll
U    test/CodeGen/PowerPC/testComparesllgeui.ll
U    test/CodeGen/Mips/llvm-ir/lh_lhu.ll
U    test/CodeGen/Mips/llvm-ir/mul.ll
U    test/CodeGen/Mips/countleading.ll
U    test/CodeGen/Mips/micromips-lwc1-swc1.ll
U    test/CodeGen/PowerPC/testComparesigeui.ll
U    test/CodeGen/Mips/llvm-ir/urem.ll
U    test/CodeGen/Mips/llvm-ir/sub.ll
U    test/CodeGen/Mips/llvm-ir/sdiv.ll
U    test/CodeGen/Mips/mips64fpldst.ll
U    test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
A    test/CodeGen/PowerPC/expand-isel-10.mir
A    test/CodeGen/PowerPC/expand-foldable-isel.ll
U    test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
U    test/CodeGen/X86/schedule-x86_32.ll
U    test/CodeGen/X86/combine-mul.ll
A    test/CodeGen/X86/fsgsbase-schedule.ll
U    test/CodeGen/PowerPC/expand-contiguous-isel.ll
U    test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
A    test/CodeGen/ARM/pr35103.ll
A    test/CodeGen/X86/clzero-schedule.ll
U    test/CodeGen/X86/avx512vl-nontemporal.ll
U    test/CodeGen/PowerPC/expand-isel.ll
U    test/CodeGen/X86/schedule-x86_64.ll
U    test/CodeGen/X86/nontemporal.ll
U    test/CodeGen/X86/fma-schedule.ll
U    test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
U    test/CodeGen/X86/avx2-nontemporal.ll
U    test/CodeGen/X86/fsgsbase.ll
U    test/CodeGen/X86/avx512-nontemporal.ll
U    include/llvm/Analysis/InstructionSimplify.h
U    include/llvm/Analysis/ConstantFolding.h
U    test/CodeGen/RISCV/addc-adde-sube-subc.ll
U    test/CodeGen/RISCV/div.ll
U    test/CodeGen/RISCV/rem.ll
U    test/CodeGen/RISCV/alu32.ll
U    test/CodeGen/RISCV/branch.ll
U    test/CodeGen/RISCV/blockaddress.ll
U    test/CodeGen/RISCV/sext-zext-trunc.ll
U    test/CodeGen/Hexagon/livephysregs-lane-masks.mir
A    test/CodeGen/X86/lwp-schedule.ll
U    test/CodeGen/RISCV/mem.ll
U    test/CodeGen/RISCV/i32-icmp.ll
U    test/CodeGen/RISCV/bare-select.ll
A    test/CodeGen/RISCV/alloca.ll
U    test/CodeGen/RISCV/shifts.ll
U    test/CodeGen/RISCV/wide-mem.ll
A    test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
A    test/CodeGen/Hexagon/intrinsics/v65-gather.ll
A    test/CodeGen/RISCV/byval.ll
U    test/CodeGen/RISCV/jumptable.ll
U    test/CodeGen/RISCV/indirectbr.ll
U    test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
A    test/CodeGen/RISCV/calling-conv.ll
U    test/CodeGen/RISCV/imm.ll
A    test/CodeGen/RISCV/calling-conv-sext-zext.ll
A    test/CodeGen/RISCV/frame.ll
U    test/CodeGen/RISCV/mul.ll
A    test/CodeGen/RISCV/fp128.ll
U    test/CodeGen/RISCV/rotl-rotr.ll
A    test/CodeGen/Hexagon/intrinsics/v65.ll
A    test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
U    include/llvm/CodeGen/SelectionDAGISel.h
U    include/llvm/ADT/TinyPtrVector.h
U    docs/CommandGuide/llvm-cov.rst
U    tools/llvm-cov/CodeCoverage.cpp
U    cmake/modules/CrossCompile.cmake
U    include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
U    tools/llvm-cov/CoverageExporterJson.cpp
A    test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/IR/IntrinsicsHexagon.td
U    docs/AMDGPUUsage.rst
U    test/CodeGen/RISCV/calls.ll
U    test/CodeGen/RISCV/select-cc.ll
U    test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
A    test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
A    test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
U    include/llvm/BinaryFormat/ELF.h
U    tools/llvm-cov/CoverageViewOptions.h
Updated to revision 320467.
UPDATING /opt/clang_commandline_docs//src/llvm/llvm/tools/clang CLANG SOURCES
Updating '.':
U    lib/CodeGen/CGCall.cpp
U    lib/Frontend/CompilerInvocation.cpp
U    lib/Basic/Targets/Mips.cpp
U    lib/Sema/SemaLambda.cpp
U    lib/Sema/SemaExprCXX.cpp
U    lib/Sema/SemaDecl.cpp
U    lib/Driver/ToolChains/Clang.cpp
U    lib/StaticAnalyzer/Checkers/CallAndMessageChecker.cpp
U    lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
U    lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
U    lib/StaticAnalyzer/Core/RegionStore.cpp
U    test/Analysis/stack-capture-leak-no-arc.mm
U    test/Analysis/stack-capture-leak-arc.mm
A    test/CXX/expr/expr.unary/expr.new/p2-cxx1z.cpp
A    test/CXX/expr/expr.unary/expr.new/p2-cxx14.cpp
U    test/CXX/expr/expr.unary/expr.new/p2-cxx0x.cpp
A    test/CodeGen/attr-mprefer-vector-width.c
U    test/CodeGen/builtins-hexagon.c
U    test/SemaCXX/warn-enum-compare.cpp
U    test/SemaCXX/warn-unused-lambda-capture.cpp
U    test/SemaCXX/enum-scoped.cpp
U    test/SemaCXX/cxx0x-initializer-stdinitializerlist.cpp
A    test/Driver/mprefer-vector-width.c
U    include/clang/Driver/Options.td
U    include/clang/StaticAnalyzer/Checkers/Checkers.td
U    include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
U    include/clang/Frontend/CodeGenOptions.h
U    include/clang/Basic/DiagnosticSemaKinds.td
U    include/clang/Basic/DiagnosticCommonKinds.td
U    include/clang/Sema/ScopeInfo.h
U    docs/ClangCommandLineReference.rst
Updated to revision 320467.
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