[Mlir-commits] [mlir] [mlir] Target Description and Cost Model in MLIR (PR #85141)

[Zhennan Qin]

ZhennanQin wrote:

Very excited to see the progress of adding target description and cost model interface into MLIR. I have below questions and comments, most of them relating to CPU devices:

1. How to initialize the target description? For host CPU, do you plan to auto-detect with CPUID? 
2. `MaxVectorWidth` is not enough for CPU, for example, for a device with AMX, if we set its `MaxVectorWidth` to 1024, it will cause trouble when generating element-wise op because element-wise op needs AVX-512 whose register width is 512. If we set `MaxVectorWidth` to 512, then we won't know if AMX is available. Do you plan to introduce other fields like `arch`(x86 or arm) and `ISAs`(AVX512 or AMX) for detection?
3. How to handle compile-time configurations like `num_threads`, `maximum_ISA`? Shall we introduce them into target description? My thinking is, target description is unique and usually read-only. It represents the nature of hardware and is shared with all compilation pipelines in parallel. For compile-time configurations, usually they're one-time configurations which only apply to the current compilation pipeline. We should manage them separately.
4. Suggest splitting hardware description with cost model interface and moving cost model interface from global context to op implementation. Because cost model factor like the `ConvAndMatMulBlockingFactor` will depend on `OP`(conv or matmul), `tensor_kind`(dense or sparse), `data_type`(BF16 or INT8), `tensor_shape`(regular or irregular), `num_threads`(balance or imbalance), `algorithm`(direct_matmul or K_slicing), `ISA_dispatch`(AVX512 or AMX). It is hard to define single factor for all of them.

https://github.com/llvm/llvm-project/pull/85141