[Mlir-commits] [mlir] [mlir][sparse] Fix sparse_generate test (PR #85009)

[Yinying Li]

https://github.com/yinying-lisa-li created https://github.com/llvm/llvm-project/pull/85009

std::uniform_int_distribution may behave differently in different system.

>From 37731f67eca73112e76ce618f42d5a73c8ed50a5 Mon Sep 17 00:00:00 2001
From: Yinying Li <yinyingli at google.com>
Date: Wed, 13 Mar 2024 01:27:20 +0000
Subject: [PATCH] fix generate

---
 .../SparseTensor/CPU/sparse_generate.mlir       | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir
index e1f73eb4ac4fe6..63a6d3acd737e2 100644
--- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir
+++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_generate.mlir
@@ -78,20 +78,13 @@ module {
     }
 
     %sv = sparse_tensor.convert %output : tensor<?xf64> to tensor<?xf64, #SparseVector>
+    %n0 = sparse_tensor.number_of_entries %sv : tensor<?xf64, #SparseVector>
 
+    // Print the number of non-zeros for verification
+    // as shuffle may generate different numbers.
     //
-    // Verify the outputs.
-    //
-    // CHECK:      ---- Sparse Tensor ----
-    // CHECK-NEXT: nse = 5
-    // CHECK-NEXT: dim = ( 50 )
-    // CHECK-NEXT: lvl = ( 50 )
-    // CHECK-NEXT: pos[0] : ( 0, 5
-    // CHECK-NEXT: crd[0] : ( 1, 9, 17, 27, 30
-    // CHECK-NEXT: values : ( 84, 34, 8, 40, 93
-    // CHECK-NEXT: ----
-    //
-    sparse_tensor.print %sv : tensor<?xf64, #SparseVector>
+    // CHECK: 5
+    vector.print %n0 : index
 
     // Release the resources.
     bufferization.dealloc_tensor %sv : tensor<?xf64, #SparseVector>