[Mlir-commits] [mlir] [MLIR][VCIX] Support VCIX intrinsics in LLVMIR dialect (PR #75875)

[Kolya Panchenko]

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+//===-- VCIX.td - VCIX dialect operation definitions *- tablegen -*--------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// The file defines the basic operations for the VCIX dialect.
+//
+// The SiFive Vector Coprocessor Interface (VCIX) provides a flexible mechanism
+// to extend application processors with custom coprocessors and
+// variable-latency arithmetic units. The interface offers throughput comparable
+// to that of standard RISC-V vector instructions. To accelerate performance,
+// system designers may use VCIX as a low-latency, high-throughput interface to
+// a coprocessor
+//
+// https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef VCIXIR_OPS
+
+include "mlir/IR/OpBase.td"
+include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
+
+//===----------------------------------------------------------------------===//
+// VCIX dialect definition.
+//===----------------------------------------------------------------------===//
+
+def VCIX_Dialect : Dialect {
+  let name = "vcix";
+  let cppNamespace = "::mlir::vcix";
+  let dependentDialects = ["LLVM::LLVMDialect"];
+  let description = [{
+     The SiFive Vector Coprocessor Interface (VCIX) provides a flexible mechanism
+     to extend application processors with custom coprocessors and
+     variable-latency arithmetic units. The interface offers throughput comparable
+     to that of standard RISC-V vector instructions. To accelerate performance,
+     system designers may use VCIX as a low-latency, high-throughput interface to
+     a coprocessor
+
+     https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
+  }];
+}
+
+// Special version for intrinsic version where int attr is zext to i32 or i64
+// depending on xlen of the target
+def VCIX_VectorOrScalar
+    : AnyTypeOf<[LLVM_AnyVector, I<64>, I<32>, F<16>, F<32>, F<64>]>;
+def VCIX_OpcodeAttr : AnyAttrOf<[I32Attr, I64Attr]>;
+def VCIX_Register : AnyTypeOf<[I32, I64]>;
+def VCIX_ImmAttr : AnyAttrOf<[I32Attr, I64Attr]>;
+def VCIX_VL : AnyTypeOf<[I<64>, I<32>]>;
+
+class VCIX_Op<string mnemonic, list<Trait> traits = []>
+    : LLVM_OpBase<VCIX_Dialect, mnemonic, traits> {
+}
+
+def VCIX_BinaryImmOp
+    : VCIX_Op<"v.iv">,
+    Results<(outs LLVM_AnyVector: $res)>,
+    Arguments<(ins VCIX_OpcodeAttr: $opcode,
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nikolaypanchenko wrote:

that's a good point. Lost them when refactored code

https://github.com/llvm/llvm-project/pull/75875