[Mlir-commits] [mlir] [mlir][spirv][webgpu] Add lowering of IAddCarry to IAdd (PR #68495)

[Jakub Kuderski]

================
@@ -133,6 +133,48 @@ Value lowerExtendedMultiplication(Operation *mulOp, PatternRewriter &rewriter,
       loc, mulOp->getResultTypes().front(), llvm::ArrayRef({low, high}));
 }
 
+Value lowerCarryAddition(Operation *addOp, PatternRewriter &rewriter, Value lhs,
+                         Value rhs) {
+  Location loc = addOp->getLoc();
+  Type argTy = lhs.getType();
+  // Emulate 64-bit addition by splitting each input element of type i32 to
+  // i16 similar to above in lowerExtendedMultiplication. We then expand
+  // to 3 additions:
+  //    - Add two low digits into low resut
+  //    - Add two high digits into high result
+  //    - Add the carry from low result to high result
----------------
kuhar wrote:

Could we calculate the carry result by comparing the sum to one of the operands?
> Member 1 of the result gets the high-order (carry) bit of the result of the addition. That is, it gets the value 1 if the addition overflowed the component width, and 0 otherwise.

I think it's something like:
```
carry := (a + b) < a ? 1 : 0
```

Where `<` is unsigned less than.

This way we wouldn't have to split the values at all.

https://github.com/llvm/llvm-project/pull/68495