[Mlir-commits] [mlir] 20bf8c4 - [mlir][SparseTensor][ArmSVE] Disable scalable vectorisation in a test

[Andrzej Warzynski]

Author: Andrzej Warzynski
Date: 2023-05-02T21:14:38Z
New Revision: 20bf8c403c5a8db6107358e534fb3ab5dd0ae9a3

URL: https://github.com/llvm/llvm-project/commit/20bf8c403c5a8db6107358e534fb3ab5dd0ae9a3
DIFF: https://github.com/llvm/llvm-project/commit/20bf8c403c5a8db6107358e534fb3ab5dd0ae9a3.diff

LOG: [mlir][SparseTensor][ArmSVE] Disable scalable vectorisation in a test

The MLIR SVE integration tests are now enabled in the
clang-aarch64-full-2stage buildbot under emulation (QEMU) and one of the
sparse integration tests is failing [1]:

  * Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir

That test is failing because we we don't have a LIT substitution to
replace:
  ```
  ; RUN: mlir-cpu-runner <command>
  ```
with
  ```
  ; RUN: <emulator> mlir-cpu-runner <command>
  ```
clang-aarch64-full-2stage does not support SVE natively and hence all
SVE integration tests require emulation. Other SVE tests use `lli` (for
which we do have the required substitution) and hence are not affected.

This patch simplifies concatenate_dim_1.mlir to always use fixed-width
vectorisation. We will re-enable scalable vectorisation once LIT
substitutions for `mlir-cpu-runner` are updated.

[1] https://lab.llvm.org/buildbot/#/builders/179/builds/6062

Added: 
    

Modified: 
    mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir
index 8607ac4539c1..9af88ba40f30 100644
--- a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir
+++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir
@@ -12,10 +12,8 @@
 // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true"
 // RUN: %{compile} | %{run}
 //
-// Do the same run, but now with direct IR generation and vectorization. Enable
-// Arm SVE if supported.
-// REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA reassociate-fp-reductions=true enable-index-optimizations=true"
-// REDEFINE: %{run_option} = %VLA_ARCH_ATTR_OPTIONS
+// Do the same run, but now with direct IR generation and vectorization.
+// REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 reassociate-fp-reductions=true enable-index-optimizations=true"
 // RUN: %{compile} | %{run}
 
 #MAT_C_C = #sparse_tensor.encoding<{dimLevelType = ["compressed", "compressed"]}>