[Mlir-commits] [mlir] 94e4928 - [mlir][sparse] minor edit in doc, removed TAB from test

[Aart Bik]

Author: Aart Bik
Date: 2022-09-30T09:42:36-07:00
New Revision: 94e4928bd365c6c7400029a8882a039ed8f6e169

URL: https://github.com/llvm/llvm-project/commit/94e4928bd365c6c7400029a8882a039ed8f6e169
DIFF: https://github.com/llvm/llvm-project/commit/94e4928bd365c6c7400029a8882a039ed8f6e169.diff

LOG: [mlir][sparse] minor edit in doc, removed TAB from test

Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D134924

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
    mlir/test/Dialect/SparseTensor/codegen.mlir

Removed: 
    


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diff  --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
index b2c27df434d88..b5a28dd599c73 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
@@ -49,21 +49,25 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding",
       In the future, we may introduce many more dimension level types and
       properties, and separate specifying the two completely rather than
       using this suffix mechanism.
-    - Dimension ordering on the indices of this tensor type. Unlike dense
-      storage, most sparse storage schemes do not provide fast random access.
+    - An optional dimension ordering on the indices of this tensor type. Unlike
+      dense storage, most sparse storage schemes do not provide fast random access.
       This affine map specifies the order of dimensions that should be supported
       by the sparse storage scheme. For example, for a 2-d tensor, "(i,j) -> (i,j)"
       requests row-wise storage and "(i,j) -> (j,i)" requests column-wise storage.
+      By default, an identify mapping is used, which implies that the original
+      indices directly correspond to stored indices (viz. "(i,j,...) -> (i,j,...)").
     - The required bit width for "pointer" storage (integral offsets into
       the sparse storage scheme). A narrow width reduces the memory footprint
       of overhead storage, as long as the width suffices to define the total
       required range (viz. the maximum number of stored entries over all indirection
-      dimensions). The choices are `8`, `16`, `32`, `64`, or `0` for a native width.
+      dimensions). The choices are `8`, `16`, `32`, `64`, or, the default, `0` to
+      indicate the native bit width.
     - The required bit width for "index" storage (elements of the coordinates of
       stored entries). A narrow width reduces the memory footprint of overhead
       storage, as long as the width suffices to define the total required range
       (viz. the maximum value of each tensor index over all dimensions). The
-      choices are `8`, `16`, `32`, `64`, or `0` for a native width.
+      choices are `8`, `16`, `32`, `64`, or, the default, `0` to indicate the
+      native bit width.
 
     Examples:
 

diff  --git a/mlir/test/Dialect/SparseTensor/codegen.mlir b/mlir/test/Dialect/SparseTensor/codegen.mlir
index 5bc7535cc13ed..b227cfc50f6ca 100644
--- a/mlir/test/Dialect/SparseTensor/codegen.mlir
+++ b/mlir/test/Dialect/SparseTensor/codegen.mlir
@@ -383,7 +383,7 @@ func.func @sparse_compression(%tensor: tensor<8x8xf64, #CSR>,
                               %filled: memref<?xi1>,
                               %added: memref<?xindex>,
                               %count: index,
-			      %i: index) {
+                              %i: index) {
   sparse_tensor.compress %values, %filled, %added, %count into %tensor[%i]
     : memref<?xf64>, memref<?xi1>, memref<?xindex>, tensor<8x8xf64, #CSR>
   return