[llvm-testresults] buildbot failure in lab.llvm.org on phase1 - sanity

llvmlab-buildmaster at lab.llvm.org llvmlab-buildmaster at lab.llvm.org
Tue Aug 12 14:39:38 PDT 2014


The Buildbot has detected a new failure on builder phase1 - sanity while building llvm.
Full details are available at:
 http://lab.llvm.org:8013/builders/phase1%20-%20sanity/builds/3536

Buildbot URL: http://lab.llvm.org:8013/

Buildslave for this Build: macpro1

Build Reason: scheduler
Build Source Stamp: 215473
Blamelist: anemet,sbenza

BUILD FAILED: failed

sincerely,
 -The Buildbot


================================================================================

CHANGES:
Files:
 include/clang/ASTMatchers/Dynamic/Parser.h
 include/clang/ASTMatchers/Dynamic/Registry.h
 include/clang/ASTMatchers/Dynamic/VariantValue.h
 lib/ASTMatchers/Dynamic/Marshallers.h
 lib/ASTMatchers/Dynamic/Parser.cpp
 lib/ASTMatchers/Dynamic/Registry.cpp
 lib/ASTMatchers/Dynamic/VariantValue.cpp
 unittests/ASTMatchers/Dynamic/ParserTest.cpp
 unittests/ASTMatchers/Dynamic/RegistryTest.cpp
On: http://10.1.1.2/svn/llvm-project
For: cfe
At: Tue 12 Aug 2014 14:25:39
Changed By: sbenza
Comments: Support named values in the autocomplete feature.

Summary:
This includes:
 - Passing a Sema to completeExpression to allow for named values in the
   expression.
 - Passing a map of names to values to the parser.
 - Update the Sema interface to include completion for matchers.
 - Change the parser to use the Sema for completion, instead of going
   directly to Registry.

Reviewers: pcc

Subscribers: klimek, cfe-commits

Differential Revision: http://reviews.llvm.org/D3509Properties: 




Files:
 lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86InstrAVX512.td
 test/CodeGen/X86/avx512-intrinsics.ll
On: http://10.1.1.2/svn/llvm-project
For: llvm
At: Tue 12 Aug 2014 14:25:39
Changed By: anemet
Comments: [AVX512] Handle valign masking intrinsic via C++ lowering

I think that this will scale better in most cases than adding a Pat<> for each
mapping from the intrinsic DAG to the intruction (i.e. rri, rrik, rrikz).  We
can just lower to the SDNode and have the resulting DAG be matches by the DAG
patterns.

Alternatively (long term), we could keep the Pat<>s but generate them via the
new AVX512_masking multiclass.  The difficulty is that in order to formulate
that we would have to concatenate DAGs.  Currently this is only supported if
the operators of the input DAGs are identical.Properties: 




LOGS:






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