[llvm-testresults] buildbot failure in lab.llvm.org on phase1 - sanity

[llvmlab-buildmaster at lab.llvm.org]

The Buildbot has detected a new failure on builder phase1 - sanity while building llvm.
Full details are available at:
 http://lab.llvm.org:8013/builders/phase1%20-%20sanity/builds/9641

Buildbot URL: http://lab.llvm.org:8013/

Buildslave for this Build: macpro1

Build Reason: scheduler
Build Source Stamp: 187492
Blamelist: delena,rsandifo

BUILD FAILED: failed

sincerely,
 -The Buildbot


================================================================================

CHANGES:
Files:
 lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrAVX512.td
 lib/Target/X86/X86InstrFragmentsSIMD.td
 lib/Target/X86/X86InstrInfo.td
 lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx512-insert-extract.ll
On: http://10.1.1.2/svn/llvm-project
For: llvm
At: Wed 31 Jul 2013 04:40:28
Changed By: delena
Comments: Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.
Properties: 




Files:
 lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
 lib/Target/SystemZ/SystemZInstrInfo.cpp
 lib/Target/SystemZ/SystemZInstrInfo.h
 lib/Target/SystemZ/SystemZInstrInfo.td
 test/CodeGen/SystemZ/addr-01.ll
 test/CodeGen/SystemZ/addr-02.ll
 test/CodeGen/SystemZ/alloca-01.ll
 test/CodeGen/SystemZ/and-02.ll
 test/CodeGen/SystemZ/and-04.ll
 test/CodeGen/SystemZ/atomicrmw-add-01.ll
 test/CodeGen/SystemZ/atomicrmw-add-02.ll
 test/CodeGen/SystemZ/atomicrmw-and-01.ll
 test/CodeGen/SystemZ/atomicrmw-and-02.ll
 test/CodeGen/SystemZ/atomicrmw-and-04.ll
 test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
 test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
 test/CodeGen/SystemZ/atomicrmw-nand-01.ll
 test/CodeGen/SystemZ/atomicrmw-nand-02.ll
 test/CodeGen/SystemZ/atomicrmw-nand-04.ll
 test/CodeGen/SystemZ/atomicrmw-or-01.ll
 test/CodeGen/SystemZ/atomicrmw-or-02.ll
 test/CodeGen/SystemZ/atomicrmw-sub-01.ll
 test/CodeGen/SystemZ/atomicrmw-sub-02.ll
 test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
 test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
 test/CodeGen/SystemZ/atomicrmw-xor-01.ll
 test/CodeGen/SystemZ/atomicrmw-xor-02.ll
 test/CodeGen/SystemZ/cmpxchg-01.ll
 test/CodeGen/SystemZ/cmpxchg-02.ll
 test/CodeGen/SystemZ/fp-move-02.ll
 test/CodeGen/SystemZ/insert-01.ll
 test/CodeGen/SystemZ/insert-02.ll
 test/CodeGen/SystemZ/risbg-01.ll
On: http://10.1.1.2/svn/llvm-project
For: llvm
At: Wed 31 Jul 2013 04:40:28
Changed By: rsandifo
Comments: [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()

r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source.  I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead.  The AND IMMEDIATE form is shorter
and is less likely to be cracked.

This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register.  The patch uses the z196 instruction RISBLG for this instead.

This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now.  Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.
Properties: 




LOGS: