[llvm-testresults] buildbot failure in smooshlab on llvm-gcc-i386-darwin9

[Jim Grosbach]

Jakob,

Assuming the bot is reasonable about the changes that went into this build, it looks like your changes are the most likely culprit here. Can you have a look?

Thanks,
-Jim


On May 25, 2010, at 5:50 PM, daniel_dunbar at apple.com wrote:

> The Buildbot has detected a new failure of llvm-gcc-i386-darwin9 on smooshlab.
> Full details are available at:
> http://smooshlab.apple.com:8010/builders/llvm-gcc-i386-darwin9/builds/6614
> 
> Buildbot URL: http://smooshlab.apple.com:8010/
> 
> Buildslave for this Build: smoosh-03.apple.com
> 
> Build Reason: 
> Build Source Stamp: 104655
> Blamelist: sliao,stoklund,void
> 
> BUILD FAILED: failed compile.llvm-gcc.stage1
> 
> sincerely,
> -The Buildbot
> 
> 
> ================================================================================
> 
> CHANGES:
> File: lib/Target/ARM/ARMCodeEmitter.cpp
> At: Tue 25 May 2010 17:30:36
> Changed By: sliao
> Comments: Adding the missing implementation of Bitfield's "clear" and "insert".
> Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.
> Properties: 
> 
> 
> 
> 
> Files:
> include/llvm/Target/Target.td
> lib/Target/ARM/ARMRegisterInfo.td
> lib/Target/Blackfin/BlackfinRegisterInfo.td
> lib/Target/MBlaze/MBlazeRegisterInfo.td
> lib/Target/MSP430/MSP430RegisterInfo.td
> lib/Target/Mips/MipsRegisterInfo.td
> lib/Target/PowerPC/PPCRegisterInfo.td
> lib/Target/Sparc/SparcRegisterInfo.td
> lib/Target/SystemZ/SystemZRegisterInfo.td
> lib/Target/X86/X86RegisterInfo.td
> utils/TableGen/RegisterInfoEmitter.cpp
> At: Tue 25 May 2010 17:35:44
> Changed By: stoklund
> Comments: Replace the SubRegSet tablegen class with a less error-prone mechanism.
> 
> A Register with subregisters must also provide SubRegIndices for adressing the
> subregisters. TableGen automatically inherits indices for sub-subregisters to
> minimize typing.
> 
> CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
> index that returns the same register, and ARM NEON Q registers where both D
> subregs have ssub_0 and ssub_1 sub-subregs.
> 
> It is now required that all subregisters are named by an index, and a future
> patch will also require inherited subregisters to be named. This is necessary to
> allow composite subregister indices to be reduced to a single index.Properties: 
> 
> 
> 
> 
> Files:
> include/llvm/CodeGen/MachineFunction.h
> lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> lib/CodeGen/StackSlotColoring.cpp
> At: Tue 25 May 2010 17:35:44
> Changed By: void
> Comments: Dale and Evan suggested putting the "check for setjmp" much earlier in the
> machine code generation. That's a good idea, so I made it so.
> Properties: 
> 
> 
> 
> 
> LOGS:
> Last 10 lines of 'stdio':
> 	./tree-ssa-threadupdate.o differs
> 	./tree-vect-analyze.o differs
> 	./tree-vect-transform.o differs
> 	./tree-vrp.o differs
> 	./tree.o differs
> 	./var-tracking.o differs
> 	./varasm.o differs
> 	make[2]: *** [compare] Error 1
> 	make[1]: *** [stage3-bubble] Error 2
> 	make: *** [all] Error 2
> 
> Last 10 lines of 'warnings':
> 	warning: structure `ipa_reference_vars_info_d' used but not defined
> 	warning: structure `reg_info_def' used but not defined
> 	warning: structure `value_set' used but not defined
> 	../../llvm-gcc.src/gcc/sched-vis.c:628: warning: no previous prototype for 'print_insn'
> 	../../llvm-gcc.src/gcc/libgcc2.c:412: warning: control reaches end of non-void function
> 	../../llvm-gcc.src/gcc/libgcc2.c:2045: warning: 'noreturn' function does return
> 	../../llvm-gcc.src/gcc/libgcc2.c:412: warning: control reaches end of non-void function
> 	../../llvm-gcc.src/gcc/libgcc2.c:2045: warning: 'noreturn' function does return
> 	warning: ./cc1-checksum.o differs
> 	warning: ./cc1plus-checksum.o differs
> 
> _______________________________________________
> llvm-testresults mailing list
> llvm-testresults at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-testresults