[llvm-testresults] X86 nightly test

[Misha Brukman]

Today's results: http://llvm.cs.uiuc.edu/testresults/X86/2006-03-25.html

DEJAGNU TEST RESULTS:
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/Bytecode/signed-intrinsics.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CFrontend/2003-08-18-SigSetJmp.c: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CodeGen/Generic/DebugStuff.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CodeGen/Generic/debug-info.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CodeGen/Generic/llvm-ct-intrinsics.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CodeGen/Generic/vector.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/CodeGen/PowerPC/cttz.ll: 
  FAIL: /home/vadve/brukman/tmp/buildtest-X86/llvm/test/Regression/Debugger/funccall.ll: 

DEJAGNU STATISTICS:
  # of expected passes		1289
  # of unexpected failures	8
  # of expected failures		37

TESTS FIXED:  

llc /SingleSource/Benchmarks/Misc-C++-EH/spirit



USERS WHO COMMITTED:
  evancheng
  jlaskey
  lattner

ADDED FILES:
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
  llvm/test/Regression/CodeGen/X86/vec_zexts2v.ll

CHANGED FILES:
  llvm/include/llvm/IntrinsicInst.h
  llvm/include/llvm/Intrinsics.h
  llvm/include/llvm/Intrinsics.td
  llvm/include/llvm/Target/MRegisterInfo.h
  llvm/include/llvm/Target/SubtargetFeature.h
  llvm/lib/CodeGen/DwarfWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.td
  llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
  llvm/lib/Target/IA64/IA64RegisterInfo.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/README.txt
  llvm/lib/Target/README.txt
  llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.td
  llvm/lib/Target/SubtargetFeature.cpp
  llvm/lib/Target/Target.td
  llvm/lib/Target/TargetSelectionDAG.td
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrMMX.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/VMCore/Function.cpp
  llvm/lib/VMCore/IntrinsicInst.cpp
  llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll
  llvm/utils/TableGen/CodeGenIntrinsics.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/DAGISelEmitter.cpp
  llvm/utils/TableGen/DAGISelEmitter.h
  llvm/utils/TableGen/IntrinsicEmitter.cpp
  llvm/utils/TableGen/RegisterInfoEmitter.cpp